1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to high-performance complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) fabricated on epitaxially grown substrates.
2. Description of the Related Art
To address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, CMOS devices are increasingly fabricated with hybrid substrates with different surface orientations that are formed using Dual Substrate Orientation (DSO) integrations. Such hybrid substrates provide PMOS and NMOS devices with their own optimized crystal orientation. In addition, while some devices exhibit performance improvement from being fabricated on semiconductor-on-insulator (SOI) substrates, others benefit from being fabricated on bulk substrates. In order to provide benefit to both device types, Bulk on SOI (BOS) integrations where bulk regions are formed in semiconductor-on-insulator (SOI) substrates are desired. Prior attempts to integrate DSO or BOS substrates have used epitaxial growth to form one of the crystal surface orientations, but the epitaxial growth process can cause epitaxial Si growth on the SOI sidewalls during epitaxial growth of the silicon on the bulk substrate, as illustrated in FIGS. 1-2. In particular, FIG. 1 shows a conventionally formed dual surface orientation wafer structure 31 in which a trench opening 6 is formed through the nitride hardmask layer 5, pad oxide layer 4, semiconductor-on-insulator (SOI) layer 3 and buried oxide layer 2 to expose the substrate 1. When epitaxial silicon 7 is grown from the substrate 1 (as depicted in FIG. 2), the epitaxial growth process simultaneously creates SOI sidewalls 8 from the exposed silicon in the SOI layer 3, thereby causing defectivity in the crystalline structure of the epitaxial silicon formed in the trench 6 where the epitaxial layers 7 and 8 meet.
Prior attempts to prevent the formation of SOI sidewalls have formed nitride sidewall spacers 9 on the sides of the trench opening 6 prior to growing epitaxial silicon from the exposed substrate 1. As shown in FIG. 3, the nitride sidewall spacers 9 are typically formed by depositing a layer of silicon nitride over the wafer structure 33 and then anisotropically etching the nitride layer so that spacers 9 remain on the sides of the trench opening 6. With the nitride sidewall spacers 9 in place, epitaxial silicon 10 can be grown from the substrate 1 in the trench opening 6 from the bottom up (as depicted in FIG. 4). However, the presence of the nitride sidewall spacers 9 can result in increased integration complexity due to the significant challenges for subsequently etching the Shallow Trench Isolation (STI) regions. In particular and as depicted in FIG. 5, when nitride hardmask regions 5, 21 (and pad oxide layers 4, 20) are used to define the STI etch regions 22, the presence of the nitride sidewall spacers 9 complicates the selection of the STI etch chemistry which must simultaneously etch silicon (from SOI layer 3 and epi layer 10), silicon dioxide (from the buried oxide layer 2) and nitride (from nitride sidewall spacers 9) while using the silicon nitride hardmask 5, 21. For example, if an STI etch process is used that is selective to nitride, the etch process will leave residual nitride spacer 9 in the STI region 22.
Accordingly, a need exists for a semiconductor manufacturing process which prevents SOI sidewalls from being formed during epitaxial growth of an epi layer from the underlying substrate. There is also a need for a fabrication process which reduces the complexity of DSO or BOS integration. In addition, there is a need for an epitaxial substrate fabrication process which simplifies the STI etch process and reduces crystalline defectivity. In addition, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.